Many semiconductor devices make use of interconnect layers that connect circuitry from electronic components formed on one layer to electronic components formed on either a different layer or a different chip to be bonded with the interconnect layer. For example, an image sensor array may be bonded to an interconnect layer that connects the individual pixels within the array to addressing circuitry that is formed on a device wafer and bonded to the interconnect layer. Each layer within the multi-layer interconnect layer may include metal lines and metal pads. The metal pads have a much larger area than the metal lines and may be used for bonding or for via landings.
During the formation of metal pads within the interconnect layer, a chemical-mechanical polishing (CMP) process is often used to level out the top of the metal pads that have been deposited into a substrate. In some cases, the CMP process causes a dishing effect in the metal pads. As the metal pads from multiple layers are formed over each other, this dishing effect accumulates. The top layer metal pads may thus have a substantial dishing affect which may cause difficulties when bonding the interconnect layer to another wafer such as a carrier wafer. Thus, it is desirable to find ways of forming interconnect layers with metal pads without the dishing effects.